This invention relates to a semiconductor memory device.
Though there have been proposed various kinds of semiconductor memory devices, it still remains as a theme of research and development to obtain such a semiconductor memory device of the type having dynamic random access memory as enjoying both high operational speed and high packing density. For example, as a MOS (metal-oxide semiconductor) type dynamic random access memory among the above-said semiconductor memory devices, so-called single-transistor memory cell is of the major trend in that field of the technology. This cell is composed of one MOS type field effect transistor (MOSFET) and one capacitor.
A memory cell of this kind is disclosed, for example, in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-7, No. 5 October 1972, pages 336 to 340. The described memories appear to have advantages in attaining high packing density owing to the small number of requisite component elements. In such memories, however, the electric charge written into a capacitor is directly detected in read-out which results in the following problems. That is, in this structure, it is required to minimize the area of the capacitor to realize large memory capacity as well as high packing density. As a result an output signal read-out from the memory is accordingly weakened in magnitude to such an extent as in the range of tens mV or hundreds mV. This means that a circuit in the succeeding stage, i.e. a sense amplifier requires to be designed as enough sensitive as detecting the minute output signal of the memory. To use such a sensitive sense amplifier demands to amplify the signals using complex clock pulses. Of course there is naturally a limit of circuit technology in augmenting the sensitivity of a sense amplifier. Particularly, considering that the short channel MOSFET's will occupy the major part of the coming semiconductor elements for memories, it will be difficult to enhance the sensitivity of a sense amplifier without degrading the operation speed. As seen from the above this kind of memory meets difficulty in realizing a memory device with high speed and high packing density.
Another example of a semiconductor memory device suited for dynamic random access is found in U.S. Pat. No. 4,161,741 issued on July 17, 1979 in which a memory cell comprises in combination MOSFET's Junction type FET's (JFET) and a capacitor so that an electrical charge stored in the capacitor is detected indirectly. Though a semiconductor memory device of this type has been improved relative to the above-mentioned prior art of the single-transistor memory cell in terms of obtaining high speed and a large read-out output, the structure of this memory to apply clock pulses to a capacitor having relatively large capacitance causes propagation delay due to interconnection line resistance and interconnection line capacitance of the wiring to apply the clock pulses to the capacitor and also due to capacitance of the storage capacitor itself, which will be a problem in attaining higher speed. Further, only depletion type MOSFET's can be used in the semiconductor memory device of this type resulting in a drawback when fabricating an integrated device with the MOSFET. Also in an aspect of reducing the size of one memory cell, this memory device is disadvantageous since it requires, in addition to the minimum component elements for a memory function, a refresh circuit which is used only after several reading-out operations.